LTC3703 [Linear Systems]
100V Synchronous Switching Regulator Controller; 100V同步开关稳压控制器
| 型号： | LTC3703 |
| 厂家： | 
Linear Systems |
| 描述： | 100V Synchronous Switching Regulator Controller |
| 文件： | 总34页 (文件大小：443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3703
100V Synchronous
Switching Regulator
Controller
FeaTures
DescripTion
The LTC®3703 is a synchronous step-down switching
regulator controller that can directly step down voltages
from up to 100V, making it ideal for telecom and automo-
tive applications. The LTC3703 drives external N-channel
MOSFETs using a constant frequency (up to 600kHz),
voltage mode architecture.
n
High Voltage Operation: Up to 100V
n
Large 1Ω Gate Drivers
n
No Current Sense Resistor Required
n
Step-Up or Step-Down DC/DC Converter
n
Dual N-Channel MOSFET Synchronous Drive
n
Excellent Line and Load Transient Response
n
Programmable Constant Frequency: 100kHz to
A precise internal reference provides 1% DC accuracy.
A high bandwidth error amplifier and patented line feed-
forward compensation provide very fast line and load
transient response. Strong 1Ω gate drivers allow the
LTC3703todrivemultipleMOSFETsforhighercurrentap-
plications.Theoperatingfrequencyisuserprogrammable
from 100kHz to 600kHz and can also be synchronized to
an external clock for noise-sensitive applications. Cur-
rent limit is programmable with an external resistor and
utilizesthevoltagedropacrossthesynchronousMOSFET
to eliminate the need for a current sense resistor. For ap-
plications requiring up to 60V operation with logic-level
MOSFETS, refer to the LTC3703-5 data sheet.
600kHz
n
1% Reference Accuracy
n
Synchronizable up to 600kHz
n
Selectable Pulse-Skip Mode Operation
n
Low Shutdown Current: 50µA Typ
n
Programmable Current Limit
n
Undervoltage Lockout
n
Programmable Soft-Start
n
16-Pin Narrow SSOP and 28-Pin SSOP Packages
applicaTions
n
48V Telecom and Base Station Power Supplies
n
Networking Equipment, Servers
PARAMETER
Maximum V
LTC3703-5
60V
LTC3703
100V
n
Automotive and Industrial Control
IN
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT and No R
MOSFET Gate Drive
4.5V to 15V
3.7V
9.3V to 15V
8.7V
are trademarks of Linear Technology Corporation. All other trademarks
SENSE
+
V
CC
V
CC
UV
UV
are the property of their respective owners. Protected by U.S. Patents, including 5408150,
5055767, 6677210, 5847554, 5481178, 6304066, 6580258.
–
3.1V
6.2V
Typical applicaTion
V
CC
9.3V TO 15V
+
V
22µF
25V
IN
Efficiency vs Load Current
BAS19
0.1µF
15V TO 100V
100
95
MODE/SYNC
V
IN
+
30k
68µF
V = 25V
IN
f
BOOST
TG
SET
V
= 50V
LTC3703
Si7456DP
IN
10k
COMP
8µH
1000pF
470pF
15k
V
= 75V
IN
V
12V
5A
OUT
FB
SW
90
+
270µF
16V
I
V
CC
MAX
8.06k
1%
10Ω
INV
DRV
CC
85
0.1µF
Si7456DP
MBR1100
RUN/SS
GND
BG
113k
1%
10µF
100Ω
2200pF
80
BGRTN
0
1
2
3
4
5
1µF
LOAD (A)
3703 F01b
3703 F01
Figure 1. High Efficiency High Voltage Step-Down Converter
3703fc
1
LTC3703
absoluTe MaxiMuM raTings (Note 1)
Supply Voltages
Peak Output Current <10µs BG,TG..............................5A
V , DRV .......................................... –0.3V to 15V
Operating Temperature Range (Note 2)
CC
CC
(DRV – BGRTN), (BOOST – SW)....... –0.3V to 15V
LTC3703E ............................................–40°C to 85°C
LTC3703I ........................................... –40°C to 125°C
LTC3703H (Note 9)............................ –40°C to 150°C
Junction Temperature (Notes 3, 7)
CC
BOOST................................................. –0.3V to 115V
BGRTN....................................................... –5V to 0V
V Voltage.............................................. –0.3V to 100V
IN
SW Voltage (Note 10).................................. –1V to 100V
RUN/SS Voltage.......................................... –0.3V to 5V
MODE/SYNC, INV Voltages....................... –0.3V to 15V
LTC3703E, LTC3703I ........................................ 125°C
LTC3703H (Note 9)........................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)..................300°C
f
, FB, I
Voltages................................ –0.3V to 3V
SET
MAX
pin conFiguraTion
TOP VIEW
V
1
2
28 BOOST
27 TG
IN
NC
TOP VIEW
NC
NC
3
26 SW
25 NC
MODE/SYNC
1
2
3
4
5
6
7
8
16
V
IN
4
f
15 B00ST
SET
NC
5
24 NC
COMP
FB
14
13
12
11
10
9
TG
MODE/SYNC
6
23 NC
f
7
22
21
NC
SW
SET
COMP
FB
8
V
CC
I
V
MAX
CC
9
20 DRV
CC
INV
RUN/SS
GND
DRV
BG
CC
I
10
11
12
13
14
19
18
17
16
15
BG
NC
NC
NC
MAX
INV
NC
BGRTN
RUN/SS
GND
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
BGRTN
T
JMAX
= 150°C, θ = 110°C/W
JA
G PACKAGE
28-LEAD PLASTIC SSOP
T
JMAX
= 125°C, θ = 100°C/W
JA
orDer inForMaTion
LEAD FREE FINISH
LTC3703EGN#PBF
LTC3703IGN#PBF
LTC3703HGN#PBF
LTC3703EG#PBF
LEAD BASED FINISH
LTC3703EGN
TAPE AND REEL
PART MARKING
3703
3703I
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 125°C
–40°C to 150°C
–40°C to 85°C
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 125°C
–40°C to 150°C
–40°C to 85°C
LTC3703EGN#TRPBF
LTC3703IGN#TRPBF
LTC3703HGN#TRPBF
LTC3703EG#TRPBF
TAPE AND REEL
LTC3703EGN#TR
LTC3703IGN#TR
LTC3703HGN#TR
LTC3703EG#TR
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
28-Lead Plastic SSOP
3703H
LTC3703EG
PART MARKING
3703
3703I
3703H
PACKAGE DESCRIPTION
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
28-Lead Plastic SSOP
LTC3703IGN
LTC3703HGN
LTC3703EG
LTC3703EG
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3703fc
2
LTC3703
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 10V, VMODE/SYNC = VINV = VSW
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
=
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
V
, DRV
V
V
V
, DRV Supply Voltage
9.3
15
100
2.5
V
V
CC
IN
CC
CC
IN
CC
Pin Voltage
I
I
I
Supply Current
V = 0V
FB
1.7
50
mA
µA
CC
CC
RUN/SS = 0V
DRV Supply Current
(Note 5)
RUN/SS = 0V
0
0
5
5
µA
µA
DRVCC
BOOST
CC
l
l
BOOST Supply Current
(Note 5) T ≤ 125°C
360
360
0
500
800
5
µA
µA
µA
J
T > 125°C
J
RUN/SS = 0V
Main Control Loop
V
Feedback Voltage
(Note 4)
0.792
0.788
0.800
0.808
0.812
V
V
FB
l
l
l
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
MODE/SYNC Threshold
MODE/SYNC Hysteresis
MODE/SYNC Current
9V < V < 15V (Note 4)
0.007
0.01
0.81
20
0.05
0.1
%/V
%
∆V
∆V
CC
FB(LINE)
FB(LOAD)
1V < V
< 2V (Note 4)
COMP
V
MODE/SYNC Rising
0.75
1
0.87
V
MODE/SYNC
mV
µA
V
∆V
MODE/SYNC
MODE/SYNC
I
0 ≤ V
≤ 15V
0
1
2
1
MODE/SYNC
V
Invert Threshold
1.5
0
INV
INV
VIN
I
I
Invert Current
0 ≤ V ≤ 15V
µA
INV
V
Sense Input Current
V
= 100V
IN
100
0
140
1
µA
µA
IN
RUN/SS = 0V, V = 10V
IN
I
I
Source Current
V = 0V
IMAX
10.5
12
13.5
µA
MAX
MAX
V
V
Offset Voltage
|V | – V
at I = 0µA
RUN/SS
–25
–25
10
10
55
65
mV
mV
OS(IMAX)
IMAX
SW
IMAX
H Grade
V
Shutdown Threshold
0.7
2.5
9
0.9
4
1.2
5.5
25
V
µA
µA
RUN/SS
RUN/SS
I
RUN/SS Source Current
Maximum RUN/SS Sink Current
Undervoltage Lockout
RUN/SS = 0V
|V | – V
≥ 200mV, V = 3V
RUN/SS
17
SW
IMAX
l
l
V
V
V
Rising
8.0
5.7
8.7
6.2
9.3
6.8
V
V
UV
CC
CC
Falling
= 25k
Oscillator
f
f
t
Oscillator Frequency
R
270
100
300
330
600
kHz
kHz
ns
OSC
SET
External Sync Frequency Range
Minimum On-Time
SYNC
200
93
ON(MIN)
DC
Maximum Duty Cycle
f < 200kHz
89
1.5
1.5
96
%
MAX
Driver
I
BG Driver Peak Source Current
2
1
2
1
A
Ω
A
BG(PEAK)
R
BG Driver Pull-Down R
(Note 8)
(Note 8)
(Note 4)
1.5
1.5
BG(SINK)
DS(ON)
I
TG Driver Peak Source Current
TG Driver Pull-Down R
TG(PEAK)
R
Ω
TG(SINK)
DS(ON)
Feedback Amplifier
Op Amp DC Open Loop Gain
A
74
5
85
25
0
dB
MHz
µA
VOL
f
I
I
Op Amp Unity Gain Crossover Frequency (Note 6)
U
FB Input Current
0 ≤ V ≤ 3V
1
FB
FB
COMP Sink/Source Current
10
mA
COMP
3703fc
3
LTC3703
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charge being delivered at the switching frequency (Q • f ).
Note 6: Guaranteed by design. Not subject to test.
G
OSC
Note 7: This IC includes overtemperature protection that is intended
Note 2: The LTC3703E is guaranteed to meet performance specifications from
0°C to 85°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls. The LTC3703I is guaranteed over the full –40°C to 125°C
operating junction temperature range. The LTC3703H is guaranteed over the
full –40°C to 150°C operating junction temperature range.
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 8: R
guaranteed by correlation to wafer level measurement.
DS(ON)
Note 9: High junction temperatures degrade operating lifetimes. Operating
lifetime at junction temperatures greater than 125°C is derated to 1000 hours.
Note 10: Transient voltages (such as due to inductive ringing) are allowed
beyond this range provided that the voltage does not exceed 10V below
ground and duration does not exceed 20ns per switching cycle.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
LTC3703: T = T + (P • 100 °C/W) G Package
J
A
D
Note 4: The LTC3703 is tested in a feedback loop that servos V to the
FB
reference voltage with the COMP pin forced to a voltage between 1V and 2V.
T = 25°C unless otherwise noted.
A
Typical perForMance characTerisTics
Efficiency vs Input Voltage
Efficiency vs Load Current
Load Transient Response
100
95
90
85
80
75
70
100
95
90
85
80
75
70
I
= 5A
OUT
V
OUT
50mV/DIV
V
= 15V
IN
V
= 45V
IN
I
= 0.5A
OUT
V
= 75V
IN
I
OUT
2A/DIV
3703 G03
V
= 5V
V
= 12V
OUT
V
V
= 50V
50µs/DIV
OUT
IN
OUT
f = 250kHz
PULSE SKIP ENABLED
f = 300kHz
PULSE SKIP DISABLED
= 12V
1A TO 5A LOAD STEP
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
0
40
INPUT VOLTAGE (V)
60 70
10 20 30
50
80
3703 G02
3703 G01
VCC Shutdown Current vs
VCC Voltage
VCC Current vs VCC Voltage
VCC Current vs Temperature
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
COMP = 1.5V
COMP = 1.5V
V
= 0V
FB
V
= 0V
FB
50 75
TEMPERATURE (°C)
125
150
–50 –25
0
25
8
10
VOLTAGE (V)
12
14
16
100
6
6
8
10
12
14
16
V
V
VOLTAGE (V)
CC
CC
3703 G05
3703 G04
3703 G06
3703fc
4
LTC3703
Typical perForMance characTerisTics
VCC Shutdown Current vs
Temperature
Reference Voltage vs
Temperature
Normalized Frequency vs
Temperature
70
65
60
55
50
45
40
35
30
0.803
0.802
0.801
0.800
0.799
0.798
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
50 75
TEMPERATURE (°C)
125
150
–50 –25
0
25
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
100
50 75
TEMPERATURE (°C)
125
150
–50 –25
0
25
100
3703 G07
3703 G09
3703 G08
Driver Peak Source Current vs
Temperature
Driver Pull-Down RDS(ON) vs
Temperature
Driver Peak Source Current vs
Supply Voltage
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 10V
V
= 10V
CC
CC
50 75
TEMPERATURE (°C)
125
50 75
125
150
100
–50 –25
0
25
150
–50 –25
0
25
100
5
6
7
8
9
10 11 12 13 14 15
TEMPERATURE (°C)
DRV /BOOST VOLTAGE (V)
CC
3703 G10
3703 G11
3703 G12
Driver Pull-Down RDS(ON) vs
Supply Voltage
Rise/Fall Time vs Gate
Capacitance
RUN/SS Pull-Up Current vs
Temperature
1.1
70
60
50
40
30
20
10
0
8
7
6
5
4
3
2
1
0
DRV , BOOST = 10V
CC
1.0
0.9
RISE
0.8
FALL
0.7
0.6
0
2000
4000
6000
8000
10000
50 75
125
150
100
6
7
8
9
10 11 12 13 14 15
–50 –25
0
25
TEMPERATURE (°C)
DRV /BOOST VOLTAGE (V)
GATE CAPACITANCE (pF)
CC
3703 G14
3703 G13
1573 G15
3703fc
5
LTC3703
Typical perForMance characTerisTics
RUN/SS Pull-Up Current vs
VCC Voltage
RUN/SS Sink Current vs
SW Voltage
Max % DC vs RUN/SS Voltage
6
5
4
3
2
1
0
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
I
= 0.3V
MAX
0
–5
–10
–10
6
8
10
12
14
16
0
0.1
0.2 0.3 0.4 0.5
|SW| VOLTAGE (V)
0.6
0.7
0.5
1.0
1.5
2.0
2.5
3.0
V
VOLTAGE (V)
RUN VOLTAGE (V)
CC
3703 G16
3703 G17
3703 G18
Max % DC vs Frequency and
Temperature
IMAX Current vs Temperature
% Duty Cycle vs COMP Voltage
100
80
60
40
20
0
13
12
11
100
95
90
85
80
75
70
V
= 10V
IN
–45°C
25°C
V
= 75V
IN
V
= 50V
IN
90°C
V
= 25V
IN
150°C
125°C
0.5
1.00 1.25 1.50
COMP (V)
1.75 2.00
0
100 200 300 400 500 600 700
FREQUENCY (kHz)
0.75
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3703 G20
3703 G21
3703 G19
Shutdown Threshold vs
Temperature
tON(MIN) vs Temperature
1.4
200
180
160
140
120
100
80
1.2
1.0
0.8
0.6
0.4
0.2
0
60
40
–50 –25
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3703 G22
0
25 50 75 100 125 150
TEMPERATURE (°C)
3703 G23
3703fc
6
LTC3703
pin FuncTions (GN16/G28)
GND (Pin 8/Pin 14): Ground Pin.
MODE/SYNC(Pin1/Pin6):Pulse-SkipModeEnable/Sync
Pin. This multifunction pin provides pulse-skip mode
enable/disable control and an external clock input for
synchronization of the internal oscillator. Pulling this pin
below 0.8V or to an external logic-level synchronization
signal disables pulse-skip mode operation and forces
continuous operation. Pulling the pin above 0.8V enables
pulse-skipmodeoperation.Thispincanalsobeconnected
to a feedback resistor divider from a secondary winding
on the inductor to regulate a second output voltage.
BGRTN (Pin 9/Pin 15): Bottom Gate Return. This pin
connects to the source of the pull-down MOSFET in the
BG driver and is normally connected to ground. Connect-
ing a negative supply to this pin allows the synchronous
MOSFET’s gate to be pulled below ground to help prevent
falseturn-onduringhighdV/dttransitionsontheSWnode.
See the Applications Information section for more details.
BG (Pin 10/Pin 19): Bottom Gate Drive. The BG pin drives
the gate of the bottom N-channel synchronous switch
f
(Pin 2/Pin 7): Frequency Set. A resistor connected
SET
MOSFET. This pin swings from BGRTN to DRV .
CC
to this pin sets the free running frequency of the internal
oscillator.SeeApplicationsInformationsectionforresistor
value selection details.
DRV (Pin 11/Pin 20): Driver Power Supply Pin. DRV
CC
CC
provides power to the BG output driver. This pin should
be connected to a voltage high enough to fully turn on
the external MOSFETs, normally 10V to 15V for standard
COMP (Pin 3/Pin 8): Loop Compensation. This pin is con-
nected directly to the output of the internal error amplifier.
An RC network is used at the COMP pin to compensate
the feedback loop for optimal transient response.
thresholdMOSFETs.DRV shouldbebypassedtoBGRTN
CC
with a 10µF, low ESR (X5R or better) ceramic capacitor.
V
(Pin 12/Pin 21): Main Supply Pin. All internal circuits
CC
FB (Pin 4/Pin 9): Feedback Input. Connect FB through a
except the output drivers are powered from this pin. V
CC
resistor divider network to V
to set the output volt-
OUT
should be connected to a low noise power supply voltage
between 9V and 15V and should be bypassed to GND
(Pin 8) with at least a 0.1µF capacitor in close proximity
to the LTC3703.
age. Also connect the loop compensation network from
COMP to FB.
I
(Pin 5/Pin 10): Current Limit Set. The I
pin sets
MAX
MAX
the current limit comparator threshold. If the voltage drop
across the bottom MOSFET exceeds the magnitude of the
SW (Pin 13/Pin 26): Switch Node Connection to Inductor
andBootstrapCapacitor.Voltageswingatthispinisfroma
voltage at I
, the controller goes into current limit. The
MAX
Schottkydiode(external)voltagedropbelowgroundtoV .
IN
I
pin has an internal 12µA current source, allowing the
MAX
TG (Pin 14/Pin 27): Top Gate Drive. The TG pin drives the
gate of the top N-channel synchronous switch MOSFET.
The TG driver draws power from the BOOST pin and
returns to the SW pin, providing true floating drive to the
top MOSFET.
current threshold to be set with a single external resistor
to ground. See the Current Limit Programming section
for more information on choosing R
.
IMAX
INV (Pin 6/Pin 11): Top/Bottom Gate Invert. Pulling this
pin above 2V sets the controller to operate in step-up
(boost) mode with the TG output driving the synchronous
MOSFETandtheBGoutputdrivingthemainswitch. Below
1V, the controller will operate in step-down (buck) mode.
BOOST (Pin 15/Pin 28): Top Gate Driver Supply. The
BOOST pin supplies power to the floating TG driver. The
BOOST pin should be bypassed to SW with a low ESR
(X5Rorbetter)0.1µFceramiccapacitor. Anadditionalfast
RUN/SS (Pin 7/Pin 13): Run/Soft-Start. Pulling RUN/SS
below 0.9V will shut down the LTC3703, turn off both of
the external MOSFET switches and reduce the quiescent
supply current to 50µA. A capacitor from RUN/SS to
ground will control the turn-on time and rate of rise of
the output voltage at power-up. An internal 4µA current
source pull-up at the RUN/SS pin sets the turn-on time
at approximately 750ms/µF.
recovery Schottky diode from DRV to BOOST will create
CC
a complete floating charge-pumped supply at BOOST.
V
IN
(Pin 16/Pin 1): Input Voltage Sense Pin. This pin is
connected to the high voltage input of the regulator and is
used by the internal feedforward compensation circuitry
to improve line regulation. This is not a supply pin.
3703fc
7
LTC3703
FuncTional DiagraM
R
SET
2
f
GN16
SET
OVERCURRENT
12µA
4µA
I
MAX
–
+
5
R
MAX
50mV
–
+
RUN/SS
–
+
5
INV
CHIP
SD
C
SS
0.9V
3.2V
UVSD OTSD
V
CC
EXT SYNC
+
–
MODE/SYNC
SYNC
DETECT
OSC
1
3
D
B
V
BOOST
TG
REVERSE
CURRENT
IN
FORCED CONTINUOUS
INV
15
14
13
C
B
COMP
M1
SW
–
DRIVE
LOGIC
PWM
+
+
–
0.8V
FB
% DC
LIMIT
+
FB
÷
DRV
CC
11
10
4
V
IN
BG
16
M2
R1
R2
MIN
MAX
–
–
+
+
BGRTN
INV
9
6
V
0.84V
0.76V
CC
(<15V)
L1
12
V
OUT
GND
OVER
TEMP
C
8
BANDGAP
V
CC
UVLO
OUT
OT SD
0.8V
REFERENCE
INTERNAL
3.2V V
UV SD
CC
V
CC
C
VCC
3703 FD
operaTion (Refer to Functional Diagram)
The LTC3703 is a constant frequency, voltage mode con-
troller for DC/DC step-down converters. It is designed to
be used in a synchronous switching architecture with two
external N-channel MOSFETs. Its high operating voltage
capability allows it to directly step down input voltages up
to100Vwithouttheneedforastep-downtransformer. For
circuit operation, please refer to the Functional Diagram
of the IC and Figure 1. The LTC3703 uses voltage mode
control in which the duty ratio is controlled directly by
the error amplifier output and thus requires no current
sense resistor. The V
pin receives the output voltage
FB
feedback and is compared to the internal 0.8V reference
by the error amplifier, which outputs an error signal at the
COMP pin. When the load current increases, it causes a
3703fc
8
LTC3703
operaTion (Refer to Functional Diagram)
drop in the feedback voltage relative to the reference. The
COMP voltage then rises, increasing the duty ratio until
the output feedback voltage again matches the reference
voltage. In normal operation, the top MOSFET is turned
on when the RS latch is set by the on-chip oscillator and
is turned off when the PWM comparator trips and resets
the latch. The PWM comparator trips at the proper duty
ratio by comparing the error amplifier output (after being
“compensated” by the line feedforward multiplier) to a
sawtooth waveform generated by the oscillator. When the
top MOSFET is turned off, the bottom MOSFET is turned
on until the next cycle begins or, if pulse-skip mode op-
eration is enabled, until the inductor current reverses as
determined by the reverse current comparator. MAX and
MIN comparators ensure that the output never exceed
V
OUT
50mV/DIV
V
IN
20V/DIV
I
L
2A/DIV
3703 F02
V
LOAD
25V TO 60V V STEP
= 12V
= 1A
20µs/DIV
OUT
I
IN
Figure 2. Line Transient Performance
Strong Gate Drivers
5% of nominal value by monitoring V and forcing the
FB
TheLTC3703containsverylowimpedancedriverscapable
of supplying amps of current to slew large MOSFET gates
quickly. Thisminimizestransitionlossesandallowsparal-
leling MOSFETs for higher current applications. A 100V
floating high side driver drives the topside MOSFET and
a low side driver drives the bottom side MOSFET (see
Figure 3). They can be powered from either a separate
DC supply or a voltage derived from the input or output
voltage(seeMOSFETDriverSuppliessection).Thebottom
outputbackintoregulationquicklybyeitherkeepingthetop
MOSFETofforforcingmaximumdutycycle.Theoperation
ofitsotherfeatures—fasttransientresponse,outstanding
lineregulation,stronggatedrivers,short-circuitprotection
and shutdown/soft-start—are described below.
Fast Transient Response
TheLTC3703usesafast25MHzopampasanerrorampli-
fier.Thisallowsthecompensationnetworktobeoptimized
for better load transient response. The high bandwidth of
the amplifier, along with high switching frequencies and
low value inductors, allow very high loop crossover fre-
quencies. The 800mV internal reference allows regulated
output voltages as low as 800mV without external level
shifting amplifiers.
side driver is supplied directly from the DRV pin. The
CC
top MOSFET drivers are biased from floating bootstrap
capacitor, C , whichnormallyisrechargedduringeachoff
B
cycle through an external diode from DRV when the top
CC
MOSFET turns off. In pulse-skip mode operation, where
it is possible that the bottom MOSFET will be off for an
extended period of time, an internal counter guarantees
that the bottom MOSFET is turned on at least once every
10 cycles for 10% of the period to refresh the bootstrap
capacitor. An undervoltage lockout keeps the LTC3703
shut down unless this voltage is above 8.7V.
Line Feedforward Compensation
TheLTC3703achievesoutstandinglinetransientresponse
using a patented feedforward correction scheme. With
this circuit the duty cycle is adjusted instantaneously to
changes in input voltage, thereby avoiding unacceptable
overshoot or undershoot. It has the added advantage of
making the DC loop gain independent of input voltage.
Figure 2 shows how large transient steps at the input have
little effect on the output voltage.
The bottom driver has an additional feature that helps
minimizethepossibilityofexternalMOSFETshoot-through.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Millercapacitance, evenwhenthebottomdriverisholding
the gate terminal at ground. If the gate is pulled up high
enough, shoot-through between the topside and bottom
3703fc
9
LTC3703
operaTion (Refer to Functional Diagram)
side MOSFETs can occur. To prevent this from occurring,
the bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up. For example, if a –2V sup-
ply is used on BGRTN, the switch node dV/dt could pull
duty cycle control set to 0%. As C continues to charge,
SS
the duty cycle is gradually increased, allowing the output
voltagetorise.Thissoft-startschemesmoothlyrampsthe
output voltage to its regulated value with no overshoot.
The RUN/SS voltage will continue ramping until it reaches
an internal 4V clamp. Then the MIN feedback comparator
is enabled and the LTC3703 is in full operation. When the
RUN/SS is low, the supply current is reduced to 50µA.
the gate up 2V before the V of the bottom MOSFET has
GS
more than 0V across it.
V
DRV
IN
CC
V
OUT
D
+
B
DRV
LTC3703
CC
BOOST
TG
C
IN
C
0V
B
NORMAL OPERATION
MT
SHUTDOWN START-UP
CURRENT
LIMIT
L
SW
V
OUT
MIN COMPARATOR ENABLED
4V
3V
OUTPUT VOLTAGE
IN REGULATION
BG
+
MB
C
OUT
RUN/SS SOFT-STARTS
OUTPUT VOLTAGE AND
INDUCTOR CURRENT
V
RUN/SS
BGRTN
0V TO –5V
1.4V
0.9V
3703 F03
MINIMUM
DUTY CYCLE
0V
Figure 3. Floating TG Driver Supply and Negative BG Return
LTC3703
POWER
ENABLE DOWN MODE
3703 F04
Constant Frequency
Figure 4. Soft-Start Operation in Start-Up and Current Limit
Theinternaloscillatorcanbeprogrammedwithanexternal
Current Limit
resistor connected from f
to ground to run between
SET
100kHz and 600kHz, thereby optimizing component size,
efficiency,andnoiseforthespecificapplication.Theinternal
oscillator can also be synchronized to an external clock
appliedtotheMODE/SYNCpinandcanlocktoafrequency
inthe100kHzto600kHzrange.Whenlockedtoanexternal
clock,pulse-skipmodeoperationisautomaticallydisabled.
Constant frequency operation brings with it a number of
benefits: inductor and capacitor values can be chosen for
a precise operating frequency and the feedback loop can
besimilarlytightlyspecified.Noisegeneratedbythecircuit
will always be at known frequencies. Subharmonic oscil-
lation and slope compensation, common headaches with
constant frequency current mode switchers, are absent in
voltage mode designs like the LTC3703.
TheLTC3703includesanonboardcurrentlimitcircuitthat
limitsthemaximumoutputcurrenttoauser-programmed
level. It works by sensing the voltage drop across the
bottom MOSFET and comparing that voltage to a user-
programmed voltage at the I
pin. Since the bottom
MAX
MOSFET looks like a low value resistor during its on-time,
the voltage drop across it is proportional to the current
flowing in it. In a buck converter, the average current in
the inductor is equal to the output current. This current
alsoflowsthroughthebottomMOSFETduringitson-time.
Thus by watching the drain-to-source voltage when the
bottomMOSFETison,theLTC3703canmonitortheoutput
current. The LTC3703 senses this voltage and inverts it to
allow it to compare the sensed voltage (which becomes
more negative as peak current increases) with a positive
Shutdown/Soft-Start
voltage at the I
pin. The I
pin includes a 12µA
MAX
MAX
pull-up, enabling the user to set the voltage at I
with
The main control loop is shut down by pulling RUN/SS
pin low. Releasing RUN/SS allows an internal 4µA current
source to charge the soft-start capacitor, C . When C
MAX
a single resistor (R
) to ground. See the Current Limit
IMAX
Programming section for R
selection.
IMAX
SS
SS
reaches 0.9V, the main control loop is enabled with the
3703fc
10
LTC3703
operaTion (Refer to Functional Diagram)
For maximum protection, the LTC3703 current limit con-
maintain regulation. The frequency drops but this further
improves efficiency by minimizing gate charge losses. In
forced continuous mode, the bottom MOSFET is always
on when the top MOSFET is off, allowing the inductor cur-
rent to reverse at low currents. This mode is less efficient
due to resistive losses, but has the advantage of better
transient response at low currents, constant frequency
operation, and the ability to maintain regulation when
sinking current. See Figure 6 for a comparison of the ef-
fect on efficiency at light loads for each mode. The MODE/
SYNC threshold is 0.8V 7.5%, allowing the MODE/SYNC
to act as a feedback pin for regulating a second winding.
If the feedback voltage drops below 0.8V, the LTC3703
reverts to continuous operation to maintain regulation in
the secondary supply.
sists of a steady-state limit circuit and an instantaneous
limit circuit. The steady-state limit circuit is a g amplifier
m
that pulls a current from the RUN/SS pin proportional
to the difference between the SW and I
voltages.
MAX
This current begins to discharge the capacitor at RUN/
SS, reducing the duty cycle and controlling the output
voltage until the current regulates at the limit. Depending
on the size of the capacitor, it may take many cycles to
dischargetheRUN/SSvoltageenoughtoproperlyregulate
the output current. This is where the instantaneous limit
circuit comes into play. The instantaneous limit circuit is
a cycle-by-cycle comparator which monitors the bottom
MOSFET’s drain voltage and keeps the top MOSFET from
turning on whenever the drain voltage is 50mV above the
programmed max drain voltage. Thus the cycle-by-cycle
comparator will keep the inductor current under control
100
V
= 25V
= 75V
90
80
70
60
50
40
30
20
10
0
IN
until the g amplifier gains control.
m
V
IN
Pulse-Skip Mode
V
= 25V
IN
The LTC3703 can operate in one of two modes selectable
with the MODE/SYNC pin—pulse-skip mode or forced
continuous mode. Pulse-skip mode is selected when in-
creased efficiency at light loads is desired. In this mode,
the bottom MOSFET is turned off when inductor current
reversestominimizetheefficiencylossduetoreversecur-
rent flow. As the load is decreased (see Figure 5), the duty
cycle is reduced to maintain regulation until its minimum
on-time (~200ns) is reached. When the load decreases
below this point, the LTC3703 begins to skip cycles to
V
= 75V
IN
FORCED CONTINUOUS
PULSE SKIP MODE
10
100
1000
10000
LOAD (mA)
3703 F06
Figure 6. Efficiency in Pulse-Skip/Forced Continuous Modes
PULSE-SKIP MODE
FORCED CONTINUOUS
DECREASING
LOAD
CURRENT
3703 F05
Figure 5. Comparison of Inductor Current Waveforms for Pulse-Skip Mode and Forced Continuous Operation
3703fc
11
LTC3703
operaTion (Refer to Functional Diagram)
Buck or Boost Mode Operation
operating mode with the following exceptions: in boost
mode, pulse-skip mode operation is always disabled
regardless of the level of the MODE/SYNC pin and the
line feedforward compensation is also disabled. The
overcurrent circuitry continues to monitor the load cur-
rent by looking at the drain voltage of the main (bottom
side) MOSFET. In boost mode, however, the peak MOS-
FET current does not equal the load current but instead
ID = ILOAD/(1 – D). This factor needs to be taken into ac-
count when programming the IMAX voltage.
The LTC3703 has the capability of operating both as a
step-down(buck)andstep-up(boost)controller.Inboost
mode, output voltages as high as 80V can be tightly regu-
lated. With the INV pin grounded, the LTC3703 operates
in buck mode with TG driving the main (topside) switch
and BG driving the synchronous (bottom side) switch.
If the INV pin is pulled above 2V, the LTC3703 operates
in boost mode with BG driving the main (bottom side)
switch and TG driving the synchronous (topside) switch.
Internal circuit operation is very similar regardless of the
applicaTions inForMaTion
ThebasicLTC3703applicationcircuitisshowninFigure 1.
External component selection is determined by the input
voltageandloadrequirementsasexplainedinthefollowing
operatingfrequencyisthatinnoise-sensitivecommunica-
tions systems, it is often desirable to keep the switching
noise out of a sensitive frequency band.
sections. After the operating frequency is selected, R
SET
The LTC3703 uses a constant frequency architecture that
can be programmed over a 100kHz to 600kHz range with
and L can be chosen. The operating frequency and the
inductor are chosen for a desired amount of ripple current
and also to optimize efficiency and component size. Next,
thepowerMOSFETsandD1areselectedbasedonvoltage,
a single resistor from the f
pin to ground, as shown
SET
in Figure 1. The nominal voltage on the f
pin is 1.2V,
SET
and the current that flows from this pin is used to charge
and discharge an internal oscillator capacitor. The value
load and efficiency requirements. C is selected for its
IN
ability to handle the large RMS currents in the converter
of R
for a given operating frequency can be chosen
SET
and C
is chosen with low enough ESR to meet the
OUT
from Figure 7 or from the following equation:
output voltage ripple and transient specifications. Finally,
the loop compensation components are chosen to meet
the desired transient specifications.
7100
RSET(kΩ)=
f(kHz)–25
1000
Operating Frequency
The choice of operating frequency and inductor value is
a trade-off between efficiency and component size. Low
frequencyoperationimprovesefficiencybyreducingMOS-
FET switching losses and gate charge losses. However,
lower frequency operation requires more inductance for a
given amount of ripple current, resulting in a larger induc-
tor size and higher cost. If the ripple current is allowed
to increase, larger output capacitors may be required to
maintain the same output ripple. For converters with high
100
10
1
200
400
600
800
1000
0
step-down V to V
ratios, another consideration is
FREQUENCY (kHz)
IN
OUT
3703 F07
the minimum on-time of the LTC3703 (see the Minimum
On-TimeConsiderationssection).Afinalconsiderationfor
Figure 7. Timing Resistor (RSET) Value
3703fc
12
LTC3703
applicaTions inForMaTion
The oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin with a frequency in
the range of 100kHz to 600kHz (refer to the MODE/SYNC
Pin section for more details). In this synchronized mode,
pulse-skipmodeoperationisdisabled.Theclockhighlevel
must exceed 2V for at least 25ns. As shown in Figure 8,
the top MOSFET turn-on will follow the rising edge of the
external clock by a constant delay equal to one-tenth of
the cycle period.
ripple current occurs at the highest V . To guarantee that
IN
ripple current does not exceed a specified maximum, the
inductor in buck mode should be chosen according to:
V
V
OUT
V
IN(MAX)
OUT
L ≥
1–
f ∆I
L(MAX)
The inductor also has an affect on low current operation
whenpulse-skipmodeoperationisenabled.Thefrequency
begins to decrease when the output current drops below
the average inductor current at which the LTC3703 is
2V TO 10V
operating at its t
in discontinuous mode (see
MODE/
SYNC
ON(MIN)
Figure 6). Lower inductance increases the peak inductor
current that occurs in each minimum on-time pulse and
thus increases the output current at which the frequency
starts decreasing.
t
= 25ns
MIN
0.8T
T
T = 1/f
O
TG
D = 40%
0.1T
Power MOSFET Selection
The LTC3703 requires at least two external N-channel
power MOSFETs, one for the top (main) switch and one or
more for the bottom (synchronous) switch. The number,
type and “on” resistance of all MOSFETs selected take into
account the voltage step-down ratio as well as the actual
position (main or synchronous) in which the MOSFET will
beused.Amuchsmallerandmuchlowerinputcapacitance
MOSFET should be used for the top MOSFET in applica-
tions that have an output voltage that is less than 1/3 of
I
L
3703 F08
Figure 8. MODE/SYNC Clock Input and Switching
Waveforms for Synchronous Operation
Inductor
the input voltage. In applications where V >> V , the
IN
OUT
The inductor in a typical LTC3703 circuit is chosen for a
specific ripple current and saturation current. Given an
input voltage range and an output voltage, the inductor
valueandoperatingfrequencydirectlydeterminetheripple
current. The inductor ripple current in the buck mode is:
top MOSFETs’ “on” resistance is normally less important
foroverallefficiencythanitsinputcapacitanceatoperating
frequencies above 300kHz. MOSFET manufacturers have
designed special purpose devices that provide reason-
ably low “on” resistance with significantly reduced input
capacitance for the main switch application in switching
regulators.
VOUT
(f)(L)
VOUT
∆IL =
1–
V
IN
Selection criteria for the power MOSFETs include the “on”
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus highest efficiency operation is obtained at
low frequency with small ripple current. To achieve this
however, requires a large inductor.
resistance R
, input capacitance, breakdown voltage
DS(ON)
and maximum output current.
Themostimportantparameterinhighvoltageapplications
is breakdown voltage BV . Both the top and bottom
DSS
MOSFETs will see full input voltage plus any additional
ringing on the switch node across its drain-to-source dur-
ing its off-time and must be chosen with the appropriate
A reasonable starting point is to choose a ripple current
between 20% and 40% of I
. Note that the largest
O(MAX)
3703fc
13
LTC3703
applicaTions inForMaTion
breakdown specification. Since many high voltage MOS-
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
FETs have higher threshold voltages (typically, V
GS(MIN)
≥ 6V), the LTC3703 is designed to be used with a 9V to
VOUT
Main Switch Duty Cycle=
15V gate drive supply (DRV pin).
CC
V
IN
For maximum efficiency, on-resistance R
capacitanceshouldbeminimized. LowR
and input
DS(ON)
V – V
IN
OUT
minimizes
Synchronous Switch Duty Cycle=
DS(ON)
V
IN
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 9).
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
VOUT
PMAIN
=
I
(
2 (1+ δ)RDS(ON)
+
MAX
)
V
V
IN
IN
I
V2 MAX (RDR)(CMILLER)•
MILLER EFFECT
V
V
GS
IN
2
a
b
+
–
V
1
1
DS
+
+
(f)
Q
V
IN
GS
V – VTH(IL) VTH(IL)
–
C
= (Q – Q )/V
DS
CC
MILLER
B
A
3703 F09
V − V
PSYNC
=
OUT (IMAX)2(1+ δ)RDS(0N)
IN
Figure 9. Gate Charge Characteristic
V
IN
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
where δ is the temperature dependency of R
, R
DS(ON) DR
is the effective top driver resistance (approximately 2Ω at
= V ), V is the drain potential and the change
V
GS
MILLER
IN
in drain potential in the particular application. V
is
TH(IL)
the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
drain current. C
is the calculated capacitance using
MILLER
the gate charge curve from the MOSFET data sheet and
the technique described above.
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
while the curve is flat) is specified for a given V drain
DS
equation includes an additional term for transition losses,
voltage, but can be adjusted for different V voltages by
DS
which peak at the highest input voltage. For V < 25V,
IN
multiplying by the ratio of the application V to the curve
DS
the high current efficiency generally improves with larger
specified V values. A way to estimate the C
term
DS
MILLER
MOSFETs, whileforV >25V, thetransitionlossesrapidly
IN
is to take the change in gate charge from points a and b
increasetothepointthattheuseofahigherR
device
DS(ON)
on a manufacturers data sheet and divide by the stated
withlowerC
actuallyprovideshigherefficiency.The
MILLER
V
DS
voltage specified. C
is the most important se-
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short circuit when the synchronous switch is on close
to 100% of the period.
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C
and C are specified sometimes but
RSS
OS
definitions of these parameters are not included.
3703fc
14
LTC3703
applicaTions inForMaTion
turethanrequired.Severalcapacitorsmayalsobeplacedin
parallel to meet size or height requirements in the design.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
vs temperature curve, and
DS(ON)
typically varies from 0.005/°C to 0.01/°C depending on
the particular MOSFET used.
BecausetantalumandOS-CONcapacitorsarenotavailable
in voltages above 30V, for regulators with input supplies
above 30V, choice of input capacitor type is limited to
ceramics or aluminum electrolytics. Ceramic capacitors
have the advantage of very low ESR and can handle high
RMS current, however ceramics with high voltage ratings
(>50V) are not available with more than a few microfarads
of capacitance. Furthermore, ceramics have high voltage
coefficients which means that the capacitance values
decrease even more when used at the rated voltage. X5R
and X7R type ceramics are recommended for their lower
voltage and temperature coefficients. Another consider-
ation when using ceramics is their high Q which if not
properly damped, may result in excessive voltage stress
onthepowerMOSFETs.Aluminumelectrolyticshavemuch
higher bulk capacitance, however, they have higher ESR
and lower RMS current ratings.
Multiple MOSFETs can be used in parallel to lower R
DS(ON)
and meet the current and thermal requirements if desired.
TheLTC3703containslargelowimpedancedriverscapable
of driving large gate capacitances without significantly
slowing transition times. In fact, when driving MOSFETs
with very low gate charge, it is sometimes helpful to slow
downthedriversbyaddingsmallgateresistors(5Ωorless)
to reduce noise and EMI caused by the fast transitions.
Schottky Diode Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power MOS-
FETs. This prevents the body diode of the bottom MOSFET
from turning on and storing charge during the dead time
and requiring a reverse recovery period that could cost
as much as 1% to 2% in efficiency. A 1A Schottky diode
is generally a good size for 3A to 5A regulators. Larger
diodes result in additional losses due to their larger junc-
tion capacitance. The diode can be omitted if the efficiency
loss can be tolerated.
A good approach is to use a combination of aluminum
electrolyticsforbulkcapacitanceandceramicsforlowESR
and RMS current. If the RMS current cannot be handled
by the aluminum capacitors alone, when used together,
the percentage of RMS current that will be supplied by the
aluminum capacitor is reduced to approximately:
Input Capacitor Selection
1
%IRMS,ALUM
≈
•100%
In continuous mode, the drain current of the top MOSFET
2
1+ (8fCRESR
)
is approximately a square wave of duty cycle V /V
OUT IN
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
where R
is the ESR of the aluminum capacitor and C
ESR
is the overall capacitance of the ceramic capacitors. Using
an aluminum electrolytic with a ceramic also helps damp
the high Q of the ceramic, minimizing ringing.
1/2
–1
VOUT
V
IN
ICIN(RMS) ≅ IO(MAX)
V
V
OUT
IN
Output Capacitor Selection
The selection of C
is primarily determined by the ESR
This formula has a maximum at V = 2V , where I =
RMS
O(MAX)
OUT
IN
OUT
required to minimize voltage ripple. The output ripple
I
/2. This simple worst-case condition is commonly
(∆V ) is approximately equal to:
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that the ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life. This makes it advisable to further derate the
capacitorortochooseacapacitorratedatahighertempera-
OUT
1
∆VOUT ≤ ∆IL ESR+
8fCOUT
3703fc
15
LTC3703
applicaTions inForMaTion
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifier. The internal reference has a guaranteed
tolerance of 1%. Tolerance of the feedback resistors will
add additional error to the output voltage. 0.1% to 1%
resistors are recommended.
Since ∆I increases with input voltage, the output ripple
L
is highest at maximum input voltage. ESR also has a sig-
nificant effect on the load transient response. Fast load
transitions at the output will appear as voltage across the
ESR of C
until the feedback loop in the LTC3703 can
OUT
change the inductor current to match the new load current
value. Typically, once the ESR requirement is satisfied the
capacitance is adequate for filtering and has the required
RMS current rating.
MOSFET Driver Supplies (DRV and BOOST)
CC
The LTC3703 drivers are supplied from the DRVCC and
BOOST pins (see Figure 3), which have an absolute
maximum voltage of 15V. If the main supply voltage,
VIN, is higher than 15V a separate supply with a voltage
between 9V and 15V must be used to power the drivers.
If a separate supply is not available, one can easily be
generated from the main supply using one of the circuits
shown in Figure 10. If the output voltage is between 10V
and 15V, the output can be used to directly power the
drivers as shown in Figure 10a. If the output is below
10V, Figure 10b shows an easy way to boost the supply
voltage to a sufficient level. This boost circuit uses the
Manufacturers such as Nichicon, Nippon Chemi-Con and
Sanyoshouldbeconsideredforhighperformancethrough-
hole capacitors. The OS-CON (organic semiconductor
dielectric) capacitor available from Sanyo has the lowest
product of ESR and size of any aluminum electrolytic at
a somewhat higher price. An additional ceramic capacitor
in parallel with OS-CON capacitors is recommended to
reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handlingandloadsteprequirements.Drytantalum,special
polymerandaluminumelectrolyticcapacitorsareavailable
in surface mount packages. Special polymer capacitors
offer very low ESR but have lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density but it is important to only use types
that have been surge tested for use in switching power
supplies. Several excellent surge-tested choices are the
AVX TPS and TPSV or the KEMET T510 series. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-driven applications providing that
consideration is given to ripple current ratings and long
term reliability. Other capacitor types include Panasonic
SP and Sanyo POSCAPs.
™
LT1613 in a ThinSOT package and a chip inductor for
minimalextraarea(<0.2in2). Two otherpossibleschemes
are an extra winding on the inductor (Figure 10c) or a
capacitive charge pump (Figure 10d). All the circuits
shown in Figure 10 require a start-up circuit (Q1, D1 and
R1) to provide driver power at initial start-up or following
a short-circuit. The resistor R1 must be sized so that it
supplies sufficient base current and zener bias current at
the lowest expected value of VIN. When using an exist-
ing supply, the supply must be capable of supplying the
requiredgatedrivercurrentwhichcanbeestimatedfrom:
I
= (f)(Q
+ Q
)
DRVCC
G(TOP)
G(BOTTOM)
This equation for I
is also useful for properly sizing
DRVCC
the circuit components shown in Figure 10.
Output Voltage
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFETs.CapacitorCBischargedthroughexternaldiode,
DB, from the DRVCC supply when SW is low. When the
topside MOSFET is turned on, the driver places the CB
voltage across the gate source of the top MOSFET. The
switch node voltage, SW, rises to VIN and the BOOST pin
follows. WiththetopsideMOSFETon, theboostvoltageis
The LTC3703 output voltage is set by a resistor divider
according to the following formula:
R1
R2
VOUT = 0.8V 1+
The external resistor divider is connected to the output as
shownintheFunctionalDiagram, allowingremotevoltage
3703fc
16
LTC3703
applicaTions inForMaTion
D2
ZHCS400
L2
10µH
V
IN
V
IN
+
C10
1µF
16V
C9
4.7µF
6.3V
1µF
R17
1M
V
SW
IN
1%
+
LT1613
C
IN
SHDN
FB
12V
+
R17
110k
1%
C
IN
GND
V
IN
V
IN
LTC3703
LTC3703
12V
TG
SW
BG
TG
SW
BG
L1
L1
V
OUT
V
OUT
<10V
10V TO
15V
V
CC
V
CC
+
C
DRV
CC
+
DRV
CC
OUT
C
OUT
BGRTN
BGRTN
3703 F10b
3703 F10a
Figure 10a. VCC Generated from 10V < VOUT < 15V
Figure 10b. VCC Generated from VOUT < 10V
V
(<40V)
IN
V
IN
+
1µF
+
C
IN
+
C
IN
OPTIONAL V
CC
CONNECTION
10V < V < 15V
SEC
12V
12V
0.22µF
BAT85
BAT85
V
IN
V
IN
LTC3703
V
LTC3703
SEC
+
+
V
TG1
SW
CC
1µF
BAT85
TG
SW
BG
VN2222LL
N
1
T1
V
DRV
FCB
OUT
CC
V
OUT
V
CC
L1
R1
R2
+
C
OUT
BG1
C
DRV
CC
OUT
GND
BGRTN
BGRTN
3703 F10c
3703 F10d
Figure 10c. Secondary Output Loop and VCC Connection
Figure 10d. Capacitive Charge Pump for VCC (VIN < 40V)
above the input supply: VBOOST = VIN + VDRVCC. The value
of the boost capacitor, CB, needs to be 100 times that
of the total input capacitance of the topside MOSFET(s).
The reverse breakdown of the external diode, DB, must be
greater than VIN(MAX). Another important consideration
for the external diode is the reverse recovery and reverse
leakage, either of which may cause excessive reverse cur-
rent to flow at full reverse voltage. If the reverse current
times reverse voltage exceeds the maximum allowable
power dissipation, the diode may be damaged. For best
results, use an ultrafast recovery silicon diode such as
the BAS19.
Aninternalundervoltagelockout(UVLO)monitorsthevolt-
age on DRV to ensure that the LTC3703 has sufficient
CC
gate drive voltage. If the DRV voltage falls below the
CC
UVLO threshold, the LTC3703 shuts down and the gate
drive outputs remain low.
3703fc
17
LTC3703
applicaTions inForMaTion
Bottom MOSFET Source Supply (BGRTN)
ambient temperature, conditions that cause the largest
power loss in the converter. Note that it is important to
checkforself-consistencybetweentheassumedMOSFET
The bottom gate driver, BG, switches from DRV to
CC
BGRTN where BGRTN can be a voltage between ground
and –5V. Why not just keep it simple and always connect
BGRTN to ground? In high voltage switching converters,
the switch node dV/dt can be many volts/ns, which will
pull up on the gate of the bottom MOSFET through its
Miller capacitance. If this Miller current, times the internal
gate resistance of the MOSFET plus the driver resistance,
exceeds the threshold of the FET, shoot-through will oc-
cur. By using a negative supply on BGRTN, the BG can be
pulledbelowgroundwhenturningthebottomMOSFEToff.
This provides a few extra volts of margin before the gate
reaches the turn-on threshold of the MOSFET. Be aware
junctiontemperatureandtheresultingvalueofI
heats the MOSFET switches.
which
LIMIT
Cautionshouldbeusedwhensettingthecurrentlimitbased
upon the R of the MOSFETs. The maximum current
DS(ON)
limitisdeterminedbytheminimumMOSFETon-resistance.
Datasheetstypicallyspecifynominalandmaximumvalues
for R
, but not a minimum. A reasonable assumption
DS(ON)
is that the minimum R
lies the same amount below
DS(ON)
the typical value as the maximum lies above it. Consult the
MOSFET manufacturer for further guidelines.
For best results, use a V
voltage between 100mV and
PROG
that the maximum voltage difference between DRV and
CC
500mV. Values outside of this range may give less accu-
BGRTNis15V.If,forexample,V
=–2V,themaximum
BGRTN
rate current limit. The current limit can also be disabled
voltage on DRV pin is now 13V instead of 15V.
CC
by floating the I
pin.
MAX
Current Limit Programming
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
Programming current limit on the LTC3703 is straight
forward. The I
pin sets the current limit by setting
MAX
the maximum allowable voltage drop across the bottom
MOSFET. The voltage across the MOSFET is set by its on-
resistance and the current flowing in the inductor, which
is the same as the output current. The LTC3703 current
limitcircuitinvertsthenegativevoltageacrosstheMOSFET
In a typical LTC3703 circuit, the feedback loop consists of
the modulator, the external inductor, the output capacitor
andthefeedbackamplifierwithitscompensationnetwork.
All of these components affect loop behavior and must be
accounted for in the loop compensation. The modulator
consists of the internal PWM generator, the output MOS-
FET drivers and the external MOSFETs themselves. From
a feedback loop point of view, it looks like a linear voltage
transferfunctionfromCOMPtoSWandhasagainroughly
equal to the input voltage. It has fairly benign AC behavior
at typical loop compensation frequencies with significant
phase shift appearing at half the switching frequency.
before comparing it to the voltage at I
current limit to be set with a positive voltage.
, allowing the
MAX
To set the current limit, calculate the expected voltage
drop across the bottom MOSFET at the maximum desired
current and maximum junction temperature:
V
= (I
)(R )(1 + δ)
DS(ON)
PROG
LIMIT
where δ is explained in the MOSFET Selection section.
is then programmed at the I pin using the
The external inductor/output capacitor combination
makes a more significant contribution to loop behavior.
These components cause a second order LC roll off at the
output, with the attendant 180° phase shift. This rolloff is
what filters the PWM waveform, resulting in the desired
DC output voltage, but the phase shift complicates the
loop compensation if the gain is still higher than unity at
the pole frequency. Eventually (usually well above the LC
pole frequency), the reactance of the output capacitor will
V
PROG
MAX
internal 12µA pull-up and an external resistor:
R
IMAX
= V /12µA
PROG
The current limit value should be checked to ensure
that I > I and also that I is
LIMIT(MIN)
OUT(MAX)
LIMIT(MAX)
less than the maximum rated current of the inductor
and bottom MOSFET. The minimum value of current
limit generally occurs with the largest V at the highest
IN
3703fc
18
LTC3703
applicaTions inForMaTion
approach its ESR and the rolloff due to the capacitor will
stop,leaving6dB/octaveand90°ofphaseshift(Figure11).
C2
C1
IN
R2
–6dB/OCT
GAIN
R1
FB
–6dB/OCT
–
R
OUT
0
FREQ
–90
B
V
+
REF
GAIN
–180
–270
–360
A
V
PHASE
–12dB/OCT
0
FREQ
–90
PHASE
–180
–270
–360
3703 F13
–6dB/OCT
Figure 13. Type 2 Schematic and Transfer Function
Type 2 loops work well in systems where the ESR zero
in the LC roll-off happens close to the LC pole, limiting
the total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple Type 1 loop.
It has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
for an extended frequency range. LTC3703 circuits using
conventional switching grade electrolytic output capaci-
tors can often get acceptable phase margin with Type 2
compensation.
3703 F11
Figure 11. Transfer Function of Buck Modulator
So far, the AC response of the loop is pretty well out
of the user’s control. The modulator is a fundamental
piece of the LTC3703 design and the external L and C are
usually chosen based on the regulation and load current
requirements without considering the AC loop response.
The feedback amplifier, on the other hand, gives us a
handle with which to adjust the AC response. The goal is
to have 180° phase shift at DC (so the loop regulates) and
something less than 360° phase shift at the point that the
loop gain falls to 0dB. The simplest strategy is to set up
the feedback amplifier as an inverting integrator, with the
0dB frequency lower than the LC pole (Figure 12). This
“Type 1” configuration is stable but transient response is
less than exceptional if the LC pole is at a low frequency.
“Type 3” loops (Figure 14) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed Type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
well above the initial LC roll-off. As with a Type 2 circuit,
the loop should cross through 0dB in the middle of the
phase bump to maximize phase margin. Many LTC3703
circuitsusinglowESRtantalumorOS-CONoutputcapaci-
torsneedType3compensationtoobtainacceptablephase
margin with a high bandwidth feedback loop.
C1
IN
GAIN
R1
FB
–
–6dB/OCT
R
B
OUT
0
FREQ
–90
V
+
REF
–180
–270
–360
IN
C2
PHASE
C1
C3
R3
R2
R1
–6dB/OCT
GAIN
3703 F12
FB
–
+6dB/OCT
–6dB/OCT
Figure 12. Type 1 Schematic and Transfer Function
R
B
OUT
0
FREQ
–90
V
+
REF
Figure 13 shows an improved “Type 2” circuit that uses
an additional pole-zero pair to temporarily remove 90°
of phase shift. This allows the loop to remain stable with
90° more phase shift in the LC section, provided the loop
reaches 0dB gain near the center of the phase “bump.”
–180
–270
–360
PHASE
3703 F14
Figure 14. Type 3 Schematic and Transfer Function
3703fc
19
LTC3703
applicaTions inForMaTion
Feedback Component Selection
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor and
MOSFET values into the following SPICE deck and gener-
Selecting the R and C values for a typical Type 2 or
Type 3 loop is a nontrivial task. The applications shown
in this data sheet show typical values, optimized for the
power components shown. They should give acceptable
performance with similar power components, but can be
way off if even one major power component is changed
significantly. Applications thatrequire optimized transient
response will require recalculation of the compensation
valuesspecificallyforthecircuitinquestion.Theunderlying
mathematics are complex, but the component values can
be calculated in a straightforward manner if we know the
gainandphaseofthemodulatoratthecrossoverfrequency.
ate an AC plot of V(V
)/V(COMP) in dB and phase of
OUT
V
in degrees. Refer to your SPICE manual for details
of how to generate this plot.
OUT
*3703 modulator gain/phase
*2003 Linear Technology
*this file written to run with PSpice 8.0
*may require modifications for other
SPICE simulators
*MOSFETs
rfet mod sw 0.02
*inductor
;MOSFET rdson
lext sw out1 10u
rl out1 out 0.015
*output cap
cout out out2 540u
resr out2 0 0.01
*3703 internals
emod mod 0 value
;inductor value
;inductor series R
Modulatorgainandphasecanbemeasureddirectlyfroma
breadboardorcanbesimulatediftheappropriateparasitic
values are known. Measurement will give more accurate
results, but simulation can often get close enough to give
a working system. To measure the modulator gain and
phase directly, wire up a breadboard with an LTC3703
and the actual MOSFETs, inductor and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close
to the LTC3703, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple Type 1 loop, with a 10k resistor from
;capacitor value
;capacitor ESR
=
{57*v(comp)}
;3703multiplier
;ac stimulus
vstim comp 0 0 ac 1
.ac dec 100 1k 1meg
.probe
.end
With the gain/phase plot in hand, a loop crossover fre-
quency can be chosen. Usually the curves look something
like Figure 11. Choose the crossover frequency in the ris-
ing or flat parts of the phase curve, beyond the external
LC poles. Frequencies between 10kHz and 50kHz usually
work well. Note the gain (GAIN, in dB) and phase (PHASE,
in degrees) at this point. The desired feedback amplifier
gain will be –GAIN to make the loop gain at 0dB at this
frequency.Nowcalculatetheneededphaseboost,assum-
ing 60° as a target phase margin:
V
to FB and a 0.1µF feedback capacitor from COMP
OUT
to FB. Choose the bias resistor, R , as required to set the
B
desired output voltage. Disconnect R from ground and
B
connect it to a signal generator or to the source output
of a network analyzer to inject a test signal into the loop.
Measure the gain and phase from the COMP pin to the
outputnodeatthepositiveterminaloftheoutputcapacitor.
Make sure the analyzer’s input is AC coupled so that the
BOOST = –(PHASE + 30°)
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
DC voltages present at both the COMP and V
nodes
OUT
don’t corrupt the measurements or damage the analyzer.
3703fc
20
LTC3703
applicaTions inForMaTion
Finally, choose a convenient resistor value for R1 (10k is
usuallyagoodvalue).Nowcalculatetheremainingvalues:
These sections discuss only the design steps specific to
a boost converter. For the design steps common to both
a buck and a boost, see the applicable section in the buck
mode section. An example of a boost converter circuit
is shown in the Typical Applications section. To operate
the LTC3703 in boost mode, the INV pin should be tied
(K is a constant used in the calculations)
f = chosen crossover frequency
(GAIN/20)
G = 10
(this converts GAIN in dB to G in
absolute gain)
to the V voltage (or a voltage above 2V). Note that in
CC
boostmode,pulse-skipoperationandthelinefeedforward
compensation are disabled.
TYPE 2 Loop:
BOOST
For a boost converter, the duty cycle of the main switch is:
K = tan
+ 45°
2
VOUT – V
IN
D=
1
C2=
VOUT
2π •f•G•K •R1
C1= C2 K2 − 1
For high V
to V ratios, the maximum V
is limited
OUT
OUT
IN
(
)
by the LTC3703’s maximum duty cycle which is typically
93%. The maximum output voltage is therefore:
K
R2=
RB =
2π •f•C1
V
IN(MIN)
VOUT(MAX)
=
≅ 14V
IN(MIN)
VREF(R1)
1–DMAX
VOUT − VREF
Boost Converter: Inductor Selection
TYPE 3 Loop:
In a boost converter, the average inductor current equals
the average input current. Thus, the maximum average
inductor current can be calculated from:
BOOST
K = tan2
+ 45°
4
1
C2=
IO(MAX)
VO
2π •f•G•R1
IL(MAX)
=
= IO(MAX) •
1− DMAX
V
IN(MIN)
C1= C2 K− 1
(
)
K
2π •f•C1
R1
Similar to a buck converter, choose the ripple current to
R2=
R3=
C3=
be 20% to 40% of I
. The ripple current amplitude
L(MAX)
then determines the inductor value as follows:
K− 1
V
L = IN(MIN) •DMAX
1
∆IL •f
2πf K • R3
Theminimumrequiredsaturationcurrentfortheinductoris:
VREF(R1)
RB =
I
> I
+ ∆I /2
L(MAX) L
VOUT − VREF
L(SAT)
Boost Converter: Power MOSFET Selection
Boost Converter Design
For information about choosing power MOSFETs for a
boostconverter, seethePowerMOSFETSelectionsection
for the buck converter, since MOSFET selection is similar.
The following sections discuss the use of the LTC3703
as a step-up (boost) converter. In boost mode, the
LTC3703 can step-up output voltages as high as 80V.
3703fc
21
LTC3703
applicaTions inForMaTion
However, note that the power dissipation equations for
the MOSFETs at maximum output current in a boost
converter are:
At lower output voltages (less than 30V), it may be pos-
sible to satisfy both the output ripple voltage and RMS
ripple current requirements with one or more capacitors
of a single capacitor type. However, at output voltages
above 30V where capacitors with both low ESR and high
bulk capacitance are hard to find, the best approach is to
use a combination of aluminum and ceramic capacitors
(see discussion in Input Capacitor section for the buck
converter). With this combination, the ripple voltage can
be improved significantly. The low ESR ceramic capaci-
tor will minimize the ESR step, while the electrolytic will
supply the required bulk capacitance.
2
IMAX
PMAIN = DMAX
1+ δ R
+
(
)
DS(ON)
1–D
MAX
2
1
2
IMAX
VOUT
R
C
•
(
DR )(
)
MILLER
1–D
MAX
1
1
+
f
( )
V – VTH(IL) VTH(IL)
CC
1
2
Boost Converter: Input Capacitor Selection
PSYNC = –
I
1+ δ R
DS(ON)
(
)
)
(
MAX
1–D
MAX
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input and the input current waveform
is continuous. The input voltage source impedance deter-
mines the size of the input capacitor, which is typically in
the range of 10µF to 100µF. A low ESR capacitor is recom-
mended though not as critical as for the output capacitor.
Boost Converter: Output Capacitor Selection
In boost mode, the output capacitor requirements are
moredemandingduetothefactthatthecurrentwaveform
is pulsed instead of continuous as in a buck converter.
The choice of component(s) is driven by the acceptable
ripple voltage which is affected by the ESR, ESL and bulk
capacitance as shown in Figure 15. The total output ripple
voltage is:
The RMS input capacitor ripple current for a boost con-
verter is:
V
IRMS(CIN) = 0.3• IN(MIN) •DMAX
L•f
1
f•C
ESR
∆VOUT = IO(MAX)
+
1–DMAX
OUT
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure
to specify surge-tested capacitors!
where the first term is due to the bulk capacitance and
second term due to the ESR.
∆V
COUT
V
OUT
(AC)
Boost Converter: Current Limit Programming
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
The LTC3703 provides current limiting in boost mode by
∆V
ESR
monitoring the V of the main switch during its on-time
DS
Figure 15. Output Voltage Ripple Waveform for a Boost Converter
and comparing it to the voltage at I
. To set the cur-
MAX
rent limit, calculate the expected voltage drop across the
MOSFET at the maximum desired inductor current and
maximum junction temperature. The maximum inductor
current is a function of both duty cycle and maximum
load current, so the limit must be set for the maximum
The choice of output capacitor is driven also by the RMS
ripple current requirement. The RMS ripple current is:
V – V
IN(MIN)
O
I
≈ I
•
RMS(COUT) O(MAX)
V
IN(MIN)
3703fc
22
LTC3703
applicaTions inForMaTion
GAIN
(dB)
PHASE
(DEG)
expected duty cycle (minimum V ) in order to ensure
IN
that the current limit does not kick in at loads < I
:
O(MAX)
GAIN
A
V
IO(MAX)
VPROG
=
=
RDS(ON)(1+ δ)
–12dB/OCT
1–DMAX
0
0
VOUT
IO(MAX) •RDS(ON)(1+ δ)
–90
–180
PHASE
V
IN(MIN)
Once V
is determined, R
is chosen as follows:
PROG
IMAX
R
IMAX
= V /12µA
PROG
3703 F16
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where V > V .
Figure 16. Transfer Function of Boost Modulator
OUT
IN
For hard shorts, the inductor current is limited only by the
input supply capability. Refer to Current Limit Program-
ming for buck mode for further considerations for current
limit programming.
compensation component to achieve this, using a Type 1
amplifier (see Figure 12), is:
–GAIN/20
G = 10
C1 = 1/(2π • f • G • R1)
Boost Converter: Feedback Loop/Compensation
Compensating a voltage mode boost converter is unfor-
tunately more difficult than for a buck converter. This is
due to an additional right-half plane (RHP) zero that is
present in the boost converter but not in a buck. The ad-
ditional phase lag resulting from the RHP zero is difficult
if not impossible to compensate even with a Type 3 loop,
so the best approach is usually to roll off the loop gain at
a lower frequency than what could be achievable in buck
converter.
Run/Soft-Start Function
The RUN/SS pin is a multipurpose pin that provide a soft-
start function and a means to shut down the LTC3703.
Soft-start reduces the input supply’s surge current by
gradually increasing the duty cycle and can also be used
for power supply sequencing.
Pulling RUN/SS below 0.9V puts the LTC3703 into a low
quiescent current shutdown (I ≅ 50µA). This pin can be
Q
drivendirectlyfromlogicasshowninFigure17. Releasing
Atypicalgain/phaseplotofavoltagemodeboostconverter
is shown in Figure 16. The modulator gain and phase can
be measured as described for a buck converter or can be
estimated as follows:
the RUN/SS pin allows an internal 4µA current source to
RUN/SS
2V/DIV
2
GAIN (COMP-to-V
DC gain) = 20Log(V
/V )
IN
OUT
OUT
V
VOUT
1
V
OUT
IN
•
Dominant Pole: f =
5V/DIV
P
2π LC
I
L
2A/DIV
Since significant phase shift begins at frequencies above
the dominant LC pole, choose a crossover frequency no
greater than about half this pole frequency. The gain of
the compensation network should equal –GAIN at this
frequency so that the overall loop gain is 0dB here. The
3703 F17
V
= 50V
2ms/DIV
IN
I
= 2A
LOAD
C
= 0.01µF
SS
Figure 17. LTC3703 Start-Up Operation
3703fc
23
LTC3703
applicaTions inForMaTion
charge up the soft-start capacitor C . When the voltage
the main output voltage and the turns ratio of the extra
winding to the primary winding as follows:
SS
on RUN/SS reaches 0.9V, the LTC3703 begins operating
at its minimum on-time. As the RUN/SS voltage increases
from 1.4V to 3V, the duty cycle is allowed to increase from
0%to100%.Thedutycyclecontrolminimizesinputsupply
inrush current and eliminates output voltage overshoot at
start-up and ensures current limit protection even with a
hardshort.TheRUN/SSvoltageisinternallyclampedat4V.
V
≈ (N + 1)V
OUT
SEC
Since the secondary winding only draws current when the
synchronous switch is on, load regulation at the auxiliary
output will be relatively good as long as the main output
is running in continuous mode. As the load on the primary
output drops and the LTC3703 switches to pulse-skip
mode operation, the auxiliary output may not be able to
maintain regulation, especially if the load on the auxiliary
output remains heavy. To avoid this, the auxiliary output
voltage can be divided down with a conventional feedback
resistor string with the divided auxiliary output voltage fed
back to the MODE/SYNC pin. The MODE/SYNC threshold
is trimmed to 800mV with 20mV of hysteresis, allowing
precisecontroloftheauxiliaryvoltageandissetasfollows:
If RUN/SS starts at 0V, the delay before starting is
approximately:
1V
4µA
tDELAY,START
=
CSS = (0.25s/µF)CSS
plus an additional delay, before the output will reach its
regulated value, of:
3V –1V
4µA
tDELAY,REG
≥
CSS = (0.5s/µF)CSS
R1
R2
VSEC(MIN) ≈ 0.8V 1+
The start delay can be reduced by using diode D1 in
Figure 18.
where R1 and R2 are shown in Figure 10c.
If the LTC3703 is operating in pulse-skip mode and the
3.3V
OR 5V
RUN/SS
RUN/SS
auxiliaryoutputvoltagedropsbelowV
,theMODE/
SEC(MIN)
D1
SYNC pin will trip and the LTC3703 will resume continu-
ous operation regardless of the load on the main output.
Thus, the MODE/SYNC pin removes the requirement that
power must be drawn from the inductor primary in order
to extract power from the auxiliary winding. With the loop
in continuous mode (MODE/SYNC < 0.8V), the auxiliary
outputs may nominally be loaded without regard to the
primary output load.
C
SS
C
SS
3703 F18
Figure 18. RUN/SS Pin Interfacing
MODE/SYNC Pin (Operating Mode and Secondary
Winding Control)
The MODE/SYNC pin is a dual function pin that can be
used for enabling or disabling pulse-skip mode operation
and also as an external clock input for synchronizing the
internal oscillator (see next section). Pulse-skip mode is
enabled when the MODE/SYNC pin is above 0.8V and is
disabled,i.e.,forcedcontinuous,whenthepinisbelow0.8V.
The following table summarizes the possible states avail-
able on the MODE/SYNC pin:
Table 1
MODE/SYNC PIN
CONDITION
DC Voltage: 0V to 0.75V
Forced Continuous
Current Reversal Enabled
In addition to providing a logic input to force continuous
operation and external synchronization, the MODE/SYNC
pin provides a means to regulate a flyback winding output
as shown in Figure 10c. The auxiliary output is taken from
a second winding on the core of the inductor, converting
it to a transformer. The auxiliary output voltage is set by
DC Voltage: ≥ 0.87V
Pulse-Skip Mode Operation
No Current Reversal
Feedback Resistors
Regulating a Secondary Winding
Ext. Clock: 0V to ≥ 2V
Forced Continuous
Current Reversal Enabled
3703fc
24
LTC3703
applicaTions inForMaTion
MODE/SYNC Pin (External Synchronization)
this minimum on-time limit and care should be taken to
ensure that:
The internal LTC3703 oscillator can be synchronized to
an external oscillator by applying and clocking the MODE/
VOUT
tON
=
> tON(MIN)
SYNCpinwithasignalabove2V . Theinternaloscillator
P-P
V •f
IN
lockstotheexternalclockafterthesecondclocktransition
is received. When external synchronization is detected,
LTC3703 will operate in forced continuous mode. If an
external clock transition is not detected for three suc-
cessive periods, the internal oscillator will revert to the
where t
is typically 200ns.
ON(MIN)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3703 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
frequency programmed by the R resistor. The internal
SET
oscillatorcansynchronizetofrequenciesbetween100kHz
and600kHz,independentofthefrequencyprogrammedby
t
for the same step-down ratio.
ON(MIN)
theR resistor.However,itisrecommendedthatanR
SET
SET
resistor be chosen such that the frequency programmed
Pin Clearance/Creepage Considerations
by the R resistor is close to the expected frequency of
SET
TheLTC3703isavailableintwopackages(GN16andG28)
both with identical functionality. The GN16 package gives
the smallest size solution, however the 0.013" (minimum)
space between pins may not provide sufficient PC board
traceclearancebetweenhighandlowvoltagepinsinhigher
voltage applications. Where clearance is an issue, the G28
package should be used. The G28 package has four un-
connected pins between the all adjacent high voltage and
low voltage pins, providing 5(0.0106") = 0.053" clearance
which will be sufficient for most applications up to 100V.
For more information, refer to the printed circuit board
design standards described in IPC-2221 (www.ipc.org).
theexternalclock.Inthisway,thebestconverteroperation
(ripple, component stress, etc) is achieved if the external
clock signal is lost.
Fault Conditions: Output Overvoltage Protection
(Crowbar)
The output overvoltage crowbar is designed to blow a
systemfuseintheinputleadwhentheoutputoftheregula-
tor rises much higher than nominal levels. This condition
causeshugecurrentstoflow, muchgreaterthaninnormal
operation. This feature is designed to protect against a
shorted top MOSFET; it does not protect against a failure
of the controller itself.
Efficiency Considerations
The comparator (MAX in the Functional Diagram) detects
overvoltage faults greater than 5% above the nominal
output voltage. When this condition is sensed the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
The efficiency of a switching regulator is equal to the out-
put power divided by the input power (x100%). Percent
efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
long as the 0V condition persists; if V
returns to a safe
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
OUT
level, normal operation automatically resumes.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time t
is the smallest amount of time
ON(MIN)
that the LTC3703 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays
and the amount of gate charge required to turn on the
top MOSFET. Low duty cycle applications may approach
losses in LTC3703 circuits: 1) LTC3703 V current, 2)
CC
2
MOSFET gate current, 3) I R losses, 4) Topside MOSFET
transition losses.
3703fc
25
LTC3703
applicaTions inForMaTion
1. V supply current. The V current is the DC supply
Transient Response
CC
CC
currentgivenintheElectricalCharacteristicstablewhich
powers the internal control circuitry of the LTC3703.
Totalsupplycurrentistypicallyabout2.5mAandusually
results in a small (<1%) loss which is proportional to
Due to the high gain error amplifier and line feedforward
compensation of the LTC3703, the output accuracy due
to DC variations in input voltage and output load current
will be almost negligible. For the few cycles following a
loadtransient,however,theoutputdeviationmaybelarger
while the feedback loop is responding. Consider a typical
48Vinputto5Voutputapplicationcircuit,subjectedtoa1A
to 5A load transient. Initially, the loop is in regulation and
the DC current in the output capacitor is zero. Suddenly,
an extra 4A (= 5A – 1A) flows out of the output capacitor
while the inductor is still supplying only 1A. This sudden
V .
CC
2. DRV current is MOSFET driver current. This current
CC
resultsfromswitchingthegatecapacitanceofthepower
MOSFETs. Each time a MOSFET gate is switched on
and then off, a packet of gate charge Q moves from
G
DRV to ground. The resulting dQ/dt is a current out
CC
of the DRV supply. In continuous mode, I
=
CC
+ Q
DRVCC
f(Q
), where Q
and Q
are
change will generate a (4A) • (R ) voltage step at the
G(TOP)
G(BOT)
G(TOP)
G(BOT)
ESR
the gate charges of the top and bottom MOSFETs.
output; with a typical 0.015Ω output capacitor ESR, this
is a 60mV step at the output.
2
3. I R losses are predicted from the DC resistances of
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
MOSFET and the synchronous MOSFET. If the two
The feedback loop will respond and will move at the
bandwidth allowed by the external compensation network
towards a new duty cycle. If the unity-gain crossover
frequency is set to 50kHz, the COMP pin will get to 60%
of the way to 90% duty cycle in 3µs. Now the inductor is
seeing 43V across itself for a large portion of the cycle
and its current will increase from 1A at a rate set by di/
dt = V/L. If the inductor value is 10µH, the peak di/dt
will be 43V/10µH or 4.3A/µs. Sometime in the next few
microseconds after the switch cycle begins, the inductor
current will have risen to the 5A level of the load current
and the output voltage will stop dropping. At this point,
the inductor current will rise somewhat above the level
of the output current to replenish the charge lost from
the output capacitor during the load transient. With a
properly compensated loop, the entire recovery time will
be inside of 10µs.
MOSFETs have approximately the same R
, then
DS(ON)
the resistance of one MOSFET can simply be summed
2
with the DCR resistance of L to obtain I R losses. For
example, if each R
= 25mΩ and R = 25mΩ, then
DS(ON)
L
total resistance is 50mΩ. This results in losses ranging
from 1% to 5% as the output current increases from
1A to 5A for a 5V output.
4. Transition losses apply only to the topside MOSFET in
buck mode and they become significant when operat-
ing at higher input voltages (typically 20V or greater).
Transition losses can be estimated from the second
term of the P
equation found in the Power MOSFET
MAIN
Selection section.
Most loads care only about the maximum deviation from
ideal, whichoccurssomewhereinthefirsttwocyclesafter
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirelycontrolledbytheESRofthecapacitorandamounts
to most of the total voltage drop. To minimize this drop,
choosealowESRcapacitorand/orparallelmultiplecapaci-
tors at the output. The capacitance value accounts for the
rest of the voltage drop until the inductor current rises.
The transition losses can become very significant at
the high end of the LTC3703 operating voltage range.
To improve efficiency, one may consider lowering the
frequency and/or using MOSFETs with lower C
at
RSS
the expense of higher R
.
DS(ON)
Other losses including C and C
ESR dissipative
OUT
IN
losses, Schottky conduction losses during dead time, and
inductor core losses generally account for less than 2%
total additional loss.
3703fc
26
LTC3703
applicaTions inForMaTion
With most output capacitors, several devices paralleled
to get the ESR down will have so much capacitance that
this drop term is negligible. Ceramic capacitors are an
exception;asmallceramiccapacitorcanhavesuitablylow
ESR with relatively small values of capacitance, making
this second drop term more significant.
V
LTC3703
OUT
R
LOAD
IRFZ44 OR
EQUIVALENT
PULSE
GENERATOR
50Ω
0V TO 10V
100Hz, 5%
DUTY CYCLE
3703 F19
Optimizing Loop Compensation
LOCATE CLOSE TO THE OUTPUT
Loopcompensationhasafundamentalimpactontransient
recovery time, the time it takes the LTC3703 to recover
after the output voltage has dropped due to a load step.
Optimizingloopcompensationentailsmaintainingthehigh-
est possible loop bandwidth while ensuring loop stability.
The feedback component selection section describes in
detail the techniques used to design an optimized Type 3
feedback loop, appropriate for most LTC3703 systems.
Figure 19. Transient Load Generator
is to take ten 1/4W film resistors and wire them in parallel
to get the desired value. This gives a noninductive resis-
tive load which can dissipate 2.5W continuously or 50W
if pulsed with a 5% duty cycle, enough for most LTC3703
circuits. Solder the MOSFET and the resistor(s) as close
to the output of the LTC3703 circuit as possible and set
up the signal generator to pulse at a 100Hz rate with a 5%
dutycycle. ThispulsestheLTC3703with500µstransients
10ms apart, adequate for viewing the entire transient
recovery time for both positive and negative transitions
while keeping the load resistor cool.
Measurement Techniques
Measuring transient response presents a challenge in
two respects: obtaining an accurate measurement and
generating a suitable transient to test the circuit. Output
measurementsshouldbetakenwithascopeprobedirectly
acrosstheoutputcapacitor.Properhighfrequencyprobing
techniques should be used. In particular, don’t use the 6"
groundleadthatcomeswiththeprobe!Useanadapterthat
fits on the tip of the probe and has a short ground clip to
ensure that inductance in the ground path doesn’t cause
a bigger spike than the transient signal being measured.
Conveniently, the typical probe tip ground clip is spaced
just right to span the leads of a typical output capacitor.
Design Example
As a design example, take a supply with the following
specifications: V = 36V to 72V (48V nominal), V
=
IN
OUT(MAX)
OUT
12V 5%, I
SET
= 10A, f = 250kHz. First, calculate
R
to give the 250kHz operating frequency:
R
SET
= 7100/(250 – 25) = 31.6k
Next, choose the inductor value for about 40% ripple
current at maximum V :
IN
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test and switch it on and off while
watching the output. If this isn’t convenient, a current
step generator is needed. This generator needs to be able
to turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC3703 and the transient generator
must be minimized.
12V
L =
12
72
1–
= 10µH
(250kHz)(0.4)(10A)
With 10µH inductor, ripple current will vary from 3.2A to
4A (32% to 40%) over the input supply range.
Next, verify that the minimum on-time is not violated. The
minimum on-time occurs at maximum V :
IN
VOUT
12
tON(MIN)
=
=
= 667ns
Figure 19 shows an example of a simple transient gen-
erator. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
V
IN(MIN)(f) 72(250kHz)
which is above the LTC3703’s 200ns minimum on-time.
3703fc
27
LTC3703
applicaTions inForMaTion
Next, choose the top and bottom MOSFET switch. Since
the drain of each MOSFET will see the full supply voltage
72V (max) plus any ringing, choose a 100V MOSFET to
output voltage changes due to inductor current ripple and
load steps. The ripple voltage will be:
∆V
= ∆I
(ESR) = (4A)(0.018Ω/2)
OUT(RIPPLE)
= 36mV
L(MAX)
provide a margin of safety. Si7456DP has a 100V BV
,
DSS
R
= 25mΩ (max), δ = 0.009/°C, C
= (19nC
DS(ON)
– 10nC)/50V = 180pF, V
MILLER
= 4.7V, θ = 20°C/W.
JA
However, a 0A to 10A load step will cause an output volt-
age change of up to:
GS(MILLER)
Thepowerdissipationcanbeestimatedatmaximuminput
voltage, assuming a junction temperature of 100°C (30°C
above an ambient of 70°C):
∆V
= ∆I
= (10A)(0.009Ω) = 90mV
OUT(STEP)
LOAD(ESR)
PC Board Layout Checklist
12
72
PMAIN
=
(10)2 1+ 0.009(100–25) (0.025)
[
]
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703.Theseitemsarealsoillustratedgraphicallyinthe
layout diagram of Figure 18. For layout of a boost mode
converter, layout is similar with V and V
Check the following in your layout:
10
2
1
1
+ (72)2
(2)(180pF)•
+
(250k)
10–4.7 4.7
= 0.70W+ 0.94W = 1.64W
swapped.
IN
OUT
And double check the assumed T in the MOSFET:
J
1. Keepthesignalandpowergroundsseparate. Thesignal
ground consists of the LTC3703 GND pin, the ground
T = 70°C + (1.64W)(20°C/W) = 103°C
J
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period
in short circuit) as the top MOSFET, use two Si7456DP
MOSFETs on the bottom:
return of C , and the (–) terminal of V . The power
VCC
OUT
groundconsistsoftheSchottkydiodeanode,thesource
of the bottom side MOSFET, and the (–) terminal of the
inputcapacitorandDRV capacitor.Connectthesignal
CC
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal
of the output capacitor as close as possible to the (–)
72− 12
PSYNC
=
(10)2 1+ 0.009(100–25) •
[
]
72
0.025
2
terminals of the input and DRV capacitor and away
CC
= 1.74W
from the Schottky loop described in (2).
2.Thehighdi/dtloopformedbythetopN-channelMOSFET,
T = 70°C + (1.74W)(20°C/W) = 105°C
J
the bottom MOSFET and the C capacitor should have
IN
Next, set the current limit resistor. Since I
= 10A, the
short leads and PC trace lengths to minimize high fre-
quencynoiseandvoltagestressfrominductiveringing.
MAX
limit should be set such that the minimum current limit is
>10A.MinimumcurrentlimitoccursatmaximumR
.
DS(ON)
3. Connect the drain of the top side MOSFET directly to the
Using the above calculation for bottom MOSFET T , the
J
(+) plate of C , and connect the source of the bottom
IN
max R
= (25mΩ/2) [1 + 0.009 (105-25)] = 21.5mΩ.
DS(ON)
side MOSFET directly to the (–) terminal of C . This
IN
Therefore,I
pinvoltageshouldbesetto(10A)(0.0215)
SET
capacitor provides the AC current to the MOSFETs.
MAX
= 0.215V. The R
resistor can now be chosen to be
4. Place the ceramic C
decoupling capacitor imme-
DRVCC
0.215V/12µA = 18k.
diately next to the IC, between DRV and BGRTN. This
CC
C
(I
is chosen for an RMS current rating of about 5A
/2) at 85°C. For the output capacitor, two low ESR
capacitor carries the MOSFET drivers’ current peaks.
IN
MAX
Likewise the C capacitor should also be next to the IC
B
OS-CON capacitors (18mΩ each) are used to minimize
between BOOST and SW.
3703fc
28
LTC3703
applicaTions inForMaTion
5. Place the small-signal components away from high
frequency switching nodes (BOOST, SW, TG, and BG).
In the layout shown in Figure 20, all the small-signal
components have been placed on one side of the IC
and all of the power components have been placed on
the other. This also helps keep the signal ground and
power ground isolated.
7. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC3703 in order
to keep the high impedance FB node short.
8. For applications with multiple switching power con-
verters connected to the same input supply, make
sure that the input filter capacitor for the LTC3703
is not shared with other converters. AC input current
from another converter could cause substantial input
voltage ripple, and this could interfere with the opera-
tion of the LTC3703. A few inches of PC trace or wire
6. A separate decoupling capacitor for the supply, V ,
CC
is useful with an RC filter between the DRV supply
CC
and V pin to filter any noise injected by the drivers.
CC
Connect this capacitor close to the IC, between the
V
and GND pins and keep the ground side of the V
CC
CC
capacitor(signalground)isolatedfromthegroundside
of the DRV capacitor (power ground).
(L ≅ 100nH) between C of the LTC3703 and the actual
CC
IN
source V should be sufficient to prevent input noise
IN
interference problems.
V
V
IN
CC
D
B
1
16
15
14
13
12
11
10
9
MODE/SYNC
V
IN
R
SET
M1
2
3
4
5
6
7
8
f
BOOST
TG
SET
+
LTC3703
R
C1
C
IN
COMP
C
B
C
C
C1
C2
FB
SW
L1
R
MAX
+
I
V
MAX
CC
R
R2
F
M2
+
INV
DRV
CC
C
C
SS
OUT
V
OUT
D1
C
RUN/SS
GND
BG
DRVCC
X5R
R1
R
C2
BGRTN
–
C
VCC
C
X5R
C3
3703 F18
Figure 20. LTC3703 Buck Converter Suggested Layout
3703fc
29
LTC3703
Typical applicaTions
36V-72V Input Voltage to 5V/10A Step-Down Converter with Pulse Skip Mode Enabled
V
CC
9.3V TO 15V
V
IN
36V TO 72V
+
22µF
25V
D
B
BAS19
1
2
3
4
5
6
7
8
16
15
14
13
12
MODE/SYNC
V
IN
C
IN
R
SET
+
68µF
100V
×2
25k
f
BOOST
TG
SET
R
C1
M1
Si7852DP
LTC3703
10k
COMP
C
B
L1
4.7µH
C
C
C1
C2
0.1µF
V
OUT
470pF
1000pF
FB
SW
5V
R
20k
10A
MAX
R2
21.5k
1%
I
V
CC
C
MAX
OUT
+
270µF
10V
×2
R 10Ω
F
11
10
9
INV
DRV
CC
M2
Si7852DP
C
SS
0.1µF
RUN/SS
GND
BG
D1
MBR1100
R1
113k
1%
C
DRVCC
R
C2
100Ω
10µF
BGRTN
C
C
C3
2200pF
VCC
1µF
3703 TA01
Single Input Supply 12V/5A Output Step-Down Converter
100Ω
*
10k
V
IN
FZT600
15V TO 80V
12V
+
22µF
25V
D
B
BAS19
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE/SYNC
V
IN
C
68µF
100V
+
IN
CMDSH-3
R
25k
12k
SET
f
BOOST
TG
SET
R
C1
M1
Si7852DP
LTC3703
10k
COMP
C
B
L1
8µH
C
C
C1
C2
0.1µF
V
OUT
470pF
1000pF
FB
SW
12V
5A
R
MAX
R2
8.06k
1%
I
V
MAX
CC
CC
+
C
OUT
R 10Ω
F
270µF
16V
INV
DRV
M2
Si7852DP
C
SS
0.1µF
RUN/SS
GND
BG
R1
113k
1%
D1
MBR1100
C
DRVCC
R
C2
100Ω
10µF
BGRTN
C
C
C3
VCC
1µF
2200pF
3703 TA02
*OPTIONAL ZENER PROVIDES UNDERVOLTAGE LOCKOUT ON INPUT SUPPLY, V
≅ 10 + V
UVLO
Z
3703fc
30
LTC3703
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
.045 .005
(4.801 – 4.978)
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 REV B 0212
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3703fc
31
LTC3703
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
RECOMMENDED SOLDER PAD LAYOUT
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12 13 14
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
(.0035 – .010)
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
TYP
(.002)
MIN
G28 SSOP 0204
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3. DRAWING NOT TO SCALE
3703fc
32
LTC3703
revision hisTory (Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
05/12 Note 10 Added.
4
3703fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC3703
Typical applicaTion
12V to 24V/5A Synchronous Boost Converter
+
D
22µF
25V
B
V
24V
5A
OUT
CMDSH-3
1
16
15
14
13
12
11
10
9
C
C
OUT2
+
OUT
MODE/SYNC
V
IN
220µF
35V
×3
10µF
50V
X5R
×2
B240A
R
SET
30.1k
2
3
4
5
6
7
8
f
BOOST
TG
SET
M1
LTC3703
10k
Si7892DP
COMP
C
B
0.1µF
L1
3.3µH
C
C1
0.1µF
100pF
V
IN
FB
SW
10V TO 15V
R
15k
SS
MAX
I
V
MAX
CC
CC
+
C
IN
R1
113k
1%
R2
3.92k
1%
R 10Ω
F
100µF
16V
INV
DRV
M2
Si7892DP
C
0.1F
RUN/SS
GND
BG
C
DRVCC
10µF
BGRTN
C
VCC
3703 TA03
1µF
L1: VISHAY IHLPSOSOEZ
: OSCON 20SP180M
C
C
: SANYO 35MV220AX
: UNITED CHEMICON
OUT1
OUT2
C
IN
NTS60X5R1H106MT
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LT®1074HV/LT1076HV Monolithic 5A/2A Step-Down DC/DC Converters
V
V
up to 60V, TO-220 and DD Packages
IN
IN
LT1339
High Power Synchronous DC/DC Controller
Dual, 2-Phase Synchronous DC/DC Controller
Synchronous Step-Down DC/DC Controller
up to 60V, Drivers 10,000pF Gate Capacitance, I
≤ 20A
OUT
LTC1702A
LTC1735
LTC1778
LT1956
550kHz Operation, No R
, 3V ≤ V ≤ 7V, I
≤ 20A
SENSE
IN
OUT
3.5V ≤ V ≤ 36V, 0.8V ≤ V
≤6V, Current Mode, I
≤ 20A
IN
OUT
OUT
No R ™ Synchronous DC/DC Controller
SENSE
4V ≤ V ≤ 36V, Fast Transient Response, Current Mode, I
≤ 20A
IN
OUT
Monolithic 1.5A, 500kHz Step-Down Regulator
50mA, 3V to 80V Linear Regulator
5.5V ≤ V ≤ 60V, 2.5mA Supply Current, 16-Pin SSOP
IN
LT3010
1.275V ≤ V
≤ 60V, No Protection Diode Required, 8-Lead MSOP
OUT
LT3430/LT3431
LT3433
Monolithic 3A, 200kHz/500kHz Step-Down Regulator 5.5V ≤ V ≤ 60V, 0.1Ω Saturation Switch, 16-Pin SSOP
IN
Monolithic Step-Up/Step-Down DC/DC Converter
4V ≤ V ≤ 60V, 500mA Switch, Automatic Step-Up/Step-Down,
IN
Single Inductor
LTC3703-5
LT3800
60V Synchronous DC/DC Controller
60V Synchronous DC/DC Controller
4V ≤ V ≤ 60V, Voltage Mode, 1Ω Logic-Level MOSFET Drivers
IN
4V ≤ V ≤ 60V, Current Mode, 1.23V ≤ V
≤ 36V
IN
OUT
3703fc
LT 0512 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
34
●
●
LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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